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Information for yosys

Versions

  • 0.9
  • 127484e
  • 0.9+4052
  • 0.9pl4081
  • 0.9.0.0.4052.ga58571d
  • 0.9 (9)
  • 0.9.r10855.9af88951b
  • 0.9+git20210616
  • 0.8
  • 0.7.0.0.826.g626b555
  • 0.7 (2)
  • 0.5.0

Package names

  • cad/yosys (2)
  • mingw-w64-i686-yosys
  • mingw-w64-x86_64-yosys
  • yosys (12)
  • yosys-dbginfo
  • yosys-devel
  • yosys-git

Repositories

Categories

  • Engineering
  • Unspecified
  • cad (2)
  • debug
  • electronics
  • extra/development
  • mingw-w64-i686-eda
  • mingw-w64-x86_64-eda
  • misc
  • office.scientific
  • programming.devel
  • universe/misc

Licenses

  • ISC (6)
  • ISC and MIT
  • MIT
  • custom:ISC

Summaries

  • A framework for RTL synthesis
  • A framework for RTL synthesis tools (mingw-w64)
  • Debug symbols for yosys
  • Development files for yosys
  • FPGA Verilog RTL synthesizer
  • Framework for Verilog RTL synthesis
  • Open RTL synthesis framework and tools
  • Open Synthesis suite
  • Open-source digital circuit synthesis suite
  • Verilog RTL Synthesis Suite
  • Yosys Open SYnthesis Suite (3)
  • Yosys Open SYnthesis Suite, including Verilog synthesizer
  • framework for Verilog RTL synthesis

Maintainers

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Build logs