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Information for yosys

Summaries

  • A framework for RTL synthesis
  • A framework for RTL synthesis tools
  • A framework for RTL synthesis tools (mingw-w64)
  • Debug symbols for yosys
  • Development files for yosys
  • FPGA Verilog RTL synthesizer
  • Framework for Verilog RTL synthesis
  • Open RTL synthesis framework and tools
  • Open Synthesis suite
  • Open-source digital circuit synthesis suite
  • Verilog RTL Synthesis Suite
  • Yosys Open SYnthesis Suite (3)
  • Yosys Open SYnthesis Suite, including Verilog synthesizer
  • framework for Verilog RTL synthesis
  • free and open source software suite for formal verification and creating FPGA bitstream and tools around this task

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